JTAG Test and ISP Software

Embedded JTAG/Boundary Scan Test and Programming

SYSTEM CASCON JTAG/Boundary Scan Software is available in four different editions: Advanced, Classic, Standard and Base. The feature set is configurable according to your needs and can be upgraded up to the most powerful edition. All software functions are accessible via an intuitive graphical user interface.

Quick Enquiry

If you want to know more about CASCON GALAXY
JTAG Test and ISP Software

The Goepel CASCON GALAXY JTAG/Boundary Scan software is based on modules with an adaptable set of features, which are all integrated into a common software interface. The CASCON GALAXY versions supports various programming and test methods.

The software provides complete handling of the serial testbus protocol so that you can focus on the test problem. Maximum automation, from reading CAD and CAE data to test program generation and documentation, is provided with the integrated tools.

Verification debugging of new hardware is also completely supported. Especially the laboratory phase benefits from the ability to test even highly complex designs up to system level at minimum effort. The system provides all features for highest productivity in laboratory, production and service.

To perfectly address the needs of development, production and customer service, the software packages are available in dedicated performance classes as Development Stations (DS) and Test/Execution Stations (TS/ES). If only In-system-programming (ISP) tasks are required, than these can be executed with CASCON POLARIS editions.

tool for Boundary scan test and programming.

  • Integrated JTAG/Boundary Scan development environment for test, verification and programming
  • JTAG/Boundary Scan programming language CASLAN with more than 150 commands
  • Library section with BSDL support and form editor for interactive model generation
  • Push button ATPG tool suite with anti ground bounce features
    Automatic fault diagnosis on cell, pin and net level
  • JTAG/Boundary Scan testability analyzer for board and system level
  • ScanVision™ – Virtual Schematic and Layout Visualizer
  •  ViPX Visual Project Explorer
  • ATPG for Processor Emulation Test and programming with VarioTAP
  • IP Embedded FPGA Instrumentation for functional test and programming with ChipVORX
  • Multi mode debugger ScanAssist™
  • Digital waveform editor
  • Integrated JTAG/Boundary Scan development environment for In-System programming (ISP)
  • ATPG for Infrastructure Test
  • Easy manual FLASH programming with CASLAN programming language
  • Automatic FLASH Program Generator (AFPG)
  • Support of SVF, JAM/ STAPL for vector import, support of IEEE-Std.1532 (2002)
  • Library section with BSDL support and form editor for interactive model generation
  • Gang- test and programming support of multiple UUTs
  • Different Editions for development and production
  • Modular and scalable software configurations
  • Full network capability / floating license / FlexLM
  • Standard JTAG/Boundary Scan Test, IEEE1149.x
  • Integrated viewers for Layout, Schematic and netlist
  • Easy integration with In-Circuit test, Flying Probes or Functional test

More than JTAG, Goepel Embedded System Access also includes:

  • Visual Project Explorer, a new Cascon user interface to present complex board and test information in a simple way.

  • A processor-specific model allows the processor to enter the debug mode. With VarioTAP individual functions (analog registers, flash access, real-time RAM tests) are addressed. Both the JTAG port and other debug interfaces are supported.

  • This method integrates the FPGA logic into the test. Even complex test applications are easy and efficient to solve with ChipVORX. Access to internal Gigabit links and other functionalities (frequency measurement, flash access, RAM tests) is possible via universal FPGA models (no separate adaption necessary).

  • JEDOS – JTAG Embedded Diagnostics Operating System for embedded test & diagnostics by functional testing in real time using the native processor. Using JEDOS (optimized for test and programming applications), complex function tests with a graphical user interface are realized. These are complete memory tests, efficient flash access or interfaces tests (Ethernet, USB …). The tests can be created in the shortest possible time without special hardware knowledge.

Visual Project Explorer (ViPX) for a Clear Overview
In the age of ever larger and more complex projects, new approaches for presentation, analysis and interaction are needed. The Visual Project Explorer (ViPX) in SYSTEM CASCON 4.7 is your new, long-awaited tool. The viewer with new user interface presents complex board and test information in a simple way. You can analyze networks in detail and interact with all elements. Only the information you really need is displayed.


ViPX Detail view of all pins & nets. Reduction to components, pins, nets for analyses, including the insertion of the TCA.


With ViPX all information is easily manageable. This also includes the display of logical interconnections beyond board boundaries. This is especially interesting if your device under test consists of several interconnected boards. See only the information you want to see – and hide those you don’t need.


ViPX – Board Level
ViPX – Simple Scan Paths
ViPX – Device Level
ViPX – Complex Scan Paths


The highlights of ViPX

  • Central user interface
  • Direct triggering of processes from the graphical user interface
  • Visualization of board data and mirroring of test and additional information (e.g. test coverage)
  • Graphical interaction at all levels (system and board level, scan path display, device network level)
  • Real, graphical elements instead of lists, input masks and tables

The VarioTAP IP technology is used to control a processor using the debug port. You use VarioTAP to access the register level of a microcontroller and use its integrated structures. You can access it via the JTAG interface or other debug interfaces (e.g. SWD or DAP).

If you are using a controller that does not support Boundary Scan, VarioTAP is a very good alternative.
The functional structure has multiple stages:

  • Flash programming both on-chip and external (e.g. eMMC, NAND, SPI Flashes)
  • functional tests (e.g. ReadADC, DDR Ram Test)
  • Own tests via open interface

In principle, all modern processors and microcontrollers are supported. Everything works in combination with the SCANFLEX hardware, which can be dynamically adjusted to the respective debug interface (JTAG, BDM, SBW, SWD, COP, etc.).

Direct access to the processor creates a universally usable test center that can perform a wide range of operations via VarioTAP control:

  • Access test of RAM (DDR2/3/4) with pin diagnosis
  • Test of bus connections and bus components
  • Test of peripheral I/Os (analog/digital)
  • Test of Gigabit interfaces (LAN, USB etc.)
  • Hardware debugging and troubleshooting
  • Flash programming (NAND/NOR, SPI, I2C)
  • Programming of microcontrollers (MCUs)
  • Customer-specific real-time tests
  • Interactive tests with boundary-scan operations

ChipVORX is an IP-based technology for implementation, access and control of Chip embedded Instruments via IEEE Std. 1149.x/JTAG. It also supports FPGA embedded instruments in the form of softcores. The ChipVORX library currently contains more than 300 different test and measurement instruments for all leading FPGA platforms. The usage of ChipVORX requires neither expert background knowledge nor specific FPGA tools or continuous IP adjustments.The FPGA-integrated ChipVORX models are functional software IPs with a modular architecture. This allows you to configure FPGAs individually to use them for functional testing. The capabilities already provided by FPGAs or CPLDs are used to increase test coverage and speed.
Which applications can ChipVORX perform?

  • High-speed in-system flash programming
  • High-speed access test of DDR-SDRAM (at-speed access)
  • Universal frequency and clock measurements
  • Bit Error Rate Test (BERT)
  • Control of IEEE-1687 instruments (IJTAG) as well as pure IEEE-1149.1 instruments
  • Interactive tests with boundary-scan operations

Emulation Based Interconnection Test – EmuBIT
Test them All! – the automatic interconnection test also reaches non-boundary-scan capable pins
An automatic connection test, the so-called Emulation Based Interconnection Test, considerably increases the test coverage of your board: by automatically integrating your microcontrollers, which are not boundary-scan capable at all.

EmuBIT utilizes the modules of a microcontroller, making the device a reliable test instrument. It emulates a boundary-scan structure in the chip, so that many pins of the microcontroller – especially the GPIO ports (General Purpose In Out ports) – can be used in the same way as with boundary scan. This automatically integrates the microcontroller into the connection test together with other boundary scan devices.

The Emulation Based Interconnection Test is based on the VarioTAP technology.

Goepel emubit
Goepel extend testcoverage using EmuBIT

Goepel Boundary Scan Technologies Overview  
Goepel ESA Software Brochure
Goepel Boundary Scan & Embedded System Acces Brochure  

Goepel Boundary Scan Design for Test Guide  
Goepel Boundary Scan Basics Brochure