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JTAG/Boundary Scan Software

Embedded JTAG/Boundary Scan Test and Programming

SYSTEM CASCON JTAG/Boundary Scan Software is available in four different editions: Advanced, Classic, Standard and Base. The feature set is configurable according to your needs and can be upgraded up to the most powerful edition. All software functions are accessible via an intuitive graphical user interface.

The Goepel CASCON GALAXY JTAG/Boundary Scan software is based on modules with an adaptable set of features, which are all integrated into a common software interface. The CASCON GALAXY versions supports various programming and test methods.

The software provides complete handling of the serial testbus protocol so that you can focus on the test problem. Maximum automation, from reading CAD and CAE data to test program generation and documentation, is provided with the integrated tools.

Verification debugging of new hardware is also completely supported. Especially the laboratory phase benefits from the ability to test even highly complex designs up to system level at minimum effort. The system provides all features for highest productivity in laboratory, production and service.

To perfectly address the needs of development, production and customer service, the software packages are available in dedicated performance classes as Development Stations (DS) and Test/Execution Stations (TS/ES). If only In-system-programming (ISP) tasks are required, than these can be executed with CASCON POLARIS editions.

CASCON GALAXY
tool for Boundary scan test and programming.

  • Integrated JTAG/Boundary Scan development environment for test, verification and programming
  • JTAG/Boundary Scan programming language CASLAN with more than 150 commands
  • Library section with BSDL support and form editor for interactive model generation
  • Push button ATPG tool suite with anti ground bounce features
    Automatic fault diagnosis on cell, pin and net level
  • JTAG/Boundary Scan testability analyzer for board and system level
  • ScanVision™ – Virtual Schematic and Layout Visualizer
  • ATPG for Processor Emulation Test and programming with VarioTAP
  • IP Embedded FPGA Instrumentation for functional test and programming with ChipVORX
  • Multi mode debugger ScanAssist™
  • Digital waveform editor
  • Integrated JTAG/Boundary Scan development environment for In-System programming (ISP)
  • ATPG for Infrastructure Test
  • Easy manual FLASH programming with CASLAN programming language
  • Automatic FLASH Program Generator (AFPG)
  • Support of SVF, JAM/ STAPL for vector import, support of IEEE-Std.1532 (2002)
  • Library section with BSDL support and form editor for interactive model generation
  • Gang- test and programming support of multiple UUTs

 CASCON POLARIS
tool for boundary scan in-system programming only.

  • Integrated JTAG/Boundary Scan development environment for In-System programming (ISP)
  • ATPG for Infrastructure Test
  • Easy manual FLASH programming with CASLAN programming language
  • Automatic FLASH Program Generator (AFPG)
  • Support of SVF, JAM/ STAPL for vector import, support of IEEE-Std.1532 (2002)
  • Library section with BSDL support and form editor for interactive model generation
  • Gang-programming support of multiple UUTs
  • Different Editions for development and production
  • Modular and scalable software configurations
  • Full network capability / floating license / FlexLM
  • Standard JTAG/Boundary Scan Test, IEEE1149.x
  • Integrated viewers for Layout, Schematic and netlist
  • Easy integration with In-Circuit test, Flying Probes or Functional test

More than JTAG, Goepel Embedded System Access also includes:


  • A processor-specific model allows the processor to enter the debug mode. With VarioTAP individual functions (analog registers, flash access, real-time RAM tests) are addressed. Both the JTAG port and other debug interfaces are supported.

  • This method integrates the FPGA logic into the test. Even complex test applications are easy and efficient to solve with ChipVORX. Access to internal Gigabit links and other functionalities (frequency measurement, flash access, RAM tests) is possible via universal FPGA models (no separate adaption necessary).

  • JEDOS – JTAG Embedded Diagnostics Operating System for embedded test & diagnostics by functional testing in real time using the native processor. Using JEDOS (optimized for test and programming applications), complex function tests with a graphical user interface are realized. These are complete memory tests, efficient flash access or interfaces tests (Ethernet, USB …). The tests can be created in the shortest possible time without special hardware knowledge.

Goepel Boundary Scan Technologies Overview  
Goepel ESA Software Brochure
Goepel Boundary Scan & Embedded System Acces Brochure  

Goepel Boundary Scan Design for Test Guide  
Goepel Boundary Scan Basics Brochure